1. Field of the Invention
The invention relates to a data processor, comprising a processing section, a control section and a communication section for information transport between said sections, said control section comprising a microcode memory and a sequencer, said communication section comprising an instruction register for storing macro-instructions each comprising an opcode an output of said instruction register being directly connected to a first input of the sequencer, said microcode memory storing a number of handlers, each of which comprises at least one micro-instruction word, a second input of said sequencer being connected to a data output of the microcode memory while a first output of said sequencer is connected to an address input of the microcode memory, said sequencer furthermore comprising an address generator for generating addresses for the microinstruction words, said address generator comprises a first and a second sub-address generator.
2. Description of the Prior Art
A data processor of this kind is known from French Patent Application No. 79 26362 (publication No. 2 440 030). The known data processor processes data, thus generating control data. The data to be processed is usually presented to the data processor in the form of instructions, mainly macro-instructions. The macro-instructions are stored in the instruction register before being processed by the data processor.
The address generator of the sequencer generates a start address for addressing a micro-instruction word which is stored in the microcode memory and which forms part of a handler. A handler contains the control data for controlling the data to be processed. The micro-instruction words of a handler contain an address field in which address data is stored for the addressing of the next micro-instruction word by the address generator. Thus, data is processed by the data processor under the control of successive micro-instruction words. The required control data is output on a further output of the microcode memory. Because the data processor must usually process data in different ways, for example read operations, arithmetic operations, write operations etc., a number of handlers are also stored in the microcode memory for this purpose. Each of these handlers in its turn contains control data for the control of a given operation. The microcode memory is subdivided into a plurality of zones which have substantially the same storage capacity. The address generator contains a first and a second sub-address generator. The first sub-address generator generates an address of a micro-instruction within a zone, whilst the second sub-address generator addresses the zone itself.
By utilizing two sub-address generators, the known data processor aims to increase the number of macro-instructions to be processed. However, it is a drawback of this set-up that the available storage capacity is inefficiently used. For example, when the microcode memory is subdivided in four zones but the macro-instruction to be processed is executed in only three steps, one unused memory location will be present in the fourth zone. Furthermore, the various micro-instruction words required for the execution of a macro-instruction are distributed among the various zones, so that very frequent jumping to another zone will occur. This time consuming, because the zones are formed on the basis of an equal distribution of the available storage capacity. The storage capacity required by a handler is not taken into account in the known data processor.